CMOS Inverter Layout

In this laboratory, I utilized Cadence Virtuoso to implement a layout cellview for a unit inverter. This required determining the correct size of the NMOS and PMOS transistors based on the FreePDK45 design process library, conforming to all design process rules, and then verifying the functionality of the layout by using Calibre Layout vs Schematic (LVS) verification.

2-Input NAND Gate Delay and Power Analysis

For this project, a 2-input NAND gate was designed and implemented in Cadence Virtuoso, and its performance characteristics were examined by utilizing SPICE simulations. The data obtained from the SPICE simulations were then tabulated, and examined to determine the effectiveness of using logical effort to to measure the propagation delay of the gate.

2-input AND gate hierarchical design using Cadence Virtuoso

In this project, I utilized Cadence Virtuoso and Formality ESP to design and test a 2-input AND gate. This gate was created using a 2-input NAND gate and an Inverter, both of which were created as independent cells.