Single Cycle MIPS Processor
For this project, I followed along a laboratory from Carnegie Mellon University, course 18-447 (Computer Architecture). This laboratory specifically entailed designing and implementing a Single-cycle MIPS processor using Verilog. To accomplish this, I first drew a basic datapath diagram to help guide my design. This diagram will be iterated upon as I implement the instructions, introducing additional control signals as required by my design. In total, 45 separate MIPS instructions were implemented. While only a subset of the entire MIPS architecture, many programs will operate correctly on this implemented processor, as the unimplemented instructions are primarily advanced math instructions. My full Verilog implementation of this processor can be shared upon request.