ECE 429 Final Project

The final project for ECE 429 involved two case studies about a 32-bit pipelined CPU design. The first case study centered around implementing several different adder designs for the ALU unit of the CPU design (Carry-Ripple, Carry-Lookahead, Carry-Select, and Carry-Skip), and analyzing the impact each design has on the overall performance of the CPU design.

Introduction to Standard Cell Based ASIC Design Flow

This laboratory is the penultimate laboratory project for the Introduction to VLSI Design course at Illinois Institute of Technology. In this project, I was introduced to the “ASIC Design Flow”, or “RTL-to-GDSII Design Flow” that is commonly used to create custom silicon/FPGA designs in an industry setting.