I am a recent Electrical Engineering graduate from Illinois Institute of Technology in Chicago. I have now started my career as a Software Engineer at Intelligent Artifacts in the New York City. In my off time, I continue to pursue my passions in Hardware Design using Chisel and FPGA devices.

Check out my resumé


  • Linux
  • VLSI Design
  • Digital Logic
  • Computer Architecture
  • Long-Distance Running
  • Exploring the City
  • Enjoying the Great Outdoors


  • B.S. Electrical Engineering, 2021

    Illinois Institute of Technology


C Programming


Scala & Chisel HDL


Git Version Control




Software Engineer

Intelligent Artifacts

Jan 2023 – Present New York City

Planned, developed, and mantained infrastructure for Intelligent Artifacts (IA) Platform. Requires building and verifying multi-stage docker images, deployment of IA Platform backend, MongoDB Database, and UI.

Incorperated new features with real-time updating functionality via SocketIO and Websockets. Improved performance of critical infrastructure by optimizing code, reducing complexity. Utilized Celery to perform long-running tasks for Flask Webapp, allowing for cancellation of task during execution.


Junior Software Engineer

Intelligent Artifacts

Feb 2022 – Dec 2022 New York City

Organize and Maintain Docker & Linux Server Infrastructure

  • Collaborate with Embedded C++ Development Team
  • Maintain Flask (Python) Web Applications
  • Utilize Git Version Control to track issues and development

ECE Laboratory Assistant

Illinois Institute of Technology

Aug 2021 – Dec 2021 Chicago

Independently supervise ECE Laboratory students during laboratory session

Responsibilities include:

  • Diagnose Issues with Student circuit design
  • Offer insight into C and C++ code for Arduino devices
  • Ensure safe operation of electronic equipment
  • Grade and provide feedback on student Pre-laboratory and Post-laboratory reports

Lab Mentor

Idea Shop Prototyping Lab

Mar 2019 – Nov 2021 Chicago

Assist students with safe operation of laboratory and prototyping equipment.

Responsibilities include:

  • Supervising Laboratory
  • Soldering and Breadboard Design
  • Circuit Debugging and Analysis
  • 3D Modelling
  • Computer Numerical Control (CNC) Machine Operation

Computer Technician

K12 Tech Repairs

Jan 2017 – Jan 2019 Indiana

Serviced a variety of computing devices for Primary and Secondary education institutions. Common devices included Chromebooks, Apple iPads, Apple Macbooks, and PC Laptops

Responsibilities include:

  • Performing component level repair of electronic devices
  • Maintaining daily device quota of 10 repairs/day
  • Develop and utilize quality control measures
  • Effectively manage stock of replacement components


Network+ Certification

Certified for Network management and general Windows Server Administration
See certificate

Recent Posts


Spring 2021 Independent Research Results

During the Spring 2021 semester, I conducted reasearch into FPGA prototyping of RISC-V SoCs with Karl Hallsby. Specifically, during the course of this project we setup and experimented with the Chipyard SoC design framework and the Xilinx Arty A7-35T FPGA in order to generate SoCs with dynamically configurable IO.

Idea Shop WebApp

During the 2021 Summer semester, I have remained at Illinois Tech to work on the development team for the Idea Shop Safety Quiz and WebApp ( This project entails utilizing the Flask Web Development Framework to implement shop safety training and live status information for the Idea Shop.

Single Cycle MIPS Processor

For this project, I followed along a laboratory from Carnegie Mellon University, course 18-447 (Computer Architecture). This laboratory specifically entailed designing and implementing a Single-cycle MIPS processor using Verilog. To accomplish this, I first drew a basic datapath diagram to help guide my design.

ECE 429 Final Project

The final project for ECE 429 involved two case studies about a 32-bit pipelined CPU design. The first case study centered around implementing several different adder designs for the ALU unit of the CPU design (Carry-Ripple, Carry-Lookahead, Carry-Select, and Carry-Skip), and analyzing the impact each design has on the overall performance of the CPU design.

Introduction to Standard Cell Based ASIC Design Flow

This laboratory is the penultimate laboratory project for the Introduction to VLSI Design course at Illinois Institute of Technology. In this project, I was introduced to the “ASIC Design Flow”, or “RTL-to-GDSII Design Flow” that is commonly used to create custom silicon/FPGA designs in an industry setting.

Basic Unix Utilities

This project required me to implement several basic Unix utilities using the C programming language. Implemented utilities include: cat, grep, zip, and unzip. Zip will be altered in a subsequent project to implement multithreading in order to improve efficiency.

CMOS Inverter Layout

In this laboratory, I utilized Cadence Virtuoso to implement a layout cellview for a unit inverter. This required determining the correct size of the NMOS and PMOS transistors based on the FreePDK45 design process library, conforming to all design process rules, and then verifying the functionality of the layout by using Calibre Layout vs Schematic (LVS) verification.

2-Input NAND Gate Delay and Power Analysis

For this project, a 2-input NAND gate was designed and implemented in Cadence Virtuoso, and its performance characteristics were examined by utilizing SPICE simulations. The data obtained from the SPICE simulations were then tabulated, and examined to determine the effectiveness of using logical effort to to measure the propagation delay of the gate.

2-input AND gate hierarchical design using Cadence Virtuoso

In this project, I utilized Cadence Virtuoso and Formality ESP to design and test a 2-input AND gate. This gate was created using a 2-input NAND gate and an Inverter, both of which were created as independent cells.

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