Spring 2021 Research Project

During the Spring 2021 semester, I am exploring Verilog and FPGA implementation of RISC-V CPU cores using the Chipyard Framework. I have been working with one other student, Karl Hallsby, on this project, with the end goal of providing a working implementation of a RISC-V processor implemented on an Arty A7-35T FPGA, and sufficient introductory documentation to create laboratories exploring RISC-V for future courses at IIT