I am a Site Reliability Engineer at Canonical. I work remotely from the New York City area. In my off time, I am a long distance runner and proud 4 time marathoner. I also continue to pursue my passions in Python application design, and hardware design in Chisel.
Check out my resumé
B.S. Electrical Engineering, 2021
Illinois Institute of Technology
Moderate
Moderate
Experienced
Planned, developed, and mantained infrastructure for Intelligent Artifacts (IA) Platform. Requires building and verifying multi-stage docker images, deployment of IA Platform backend, MongoDB Database, and UI.
Incorperated new features with real-time updating functionality via SocketIO and Websockets. Improved performance of critical infrastructure by optimizing code, reducing complexity. Utilized Celery to perform long-running tasks for Flask Webapp, allowing for cancellation of task during execution.
Organize and Maintain Docker & Linux Server Infrastructure
Independently supervise ECE Laboratory students during laboratory session
Responsibilities include:
Assist students with safe operation of laboratory and prototyping equipment.
Responsibilities include:
During the Spring 2021 semester, I conducted reasearch into FPGA prototyping of RISC-V SoCs with Karl Hallsby. Specifically, during the course of this project we setup and experimented with the Chipyard SoC design framework and the Xilinx Arty A7-35T FPGA in order to generate SoCs with dynamically configurable IO.
During the 2021 Summer semester, I have remained at Illinois Tech to work on the development team for the Idea Shop Safety Quiz and WebApp (https://ideashop.iit.edu). This project entails utilizing the Flask Web Development Framework to implement shop safety training and live status information for the Idea Shop.
For this project, I followed along a laboratory from Carnegie Mellon University, course 18-447 (Computer Architecture). This laboratory specifically entailed designing and implementing a Single-cycle MIPS processor using Verilog. To accomplish this, I first drew a basic datapath diagram to help guide my design.
The final project for ECE 429 involved two case studies about a 32-bit pipelined CPU design. The first case study centered around implementing several different adder designs for the ALU unit of the CPU design (Carry-Ripple, Carry-Lookahead, Carry-Select, and Carry-Skip), and analyzing the impact each design has on the overall performance of the CPU design.
This laboratory is the penultimate laboratory project for the Introduction to VLSI Design course at Illinois Institute of Technology. In this project, I was introduced to the “ASIC Design Flow”, or “RTL-to-GDSII Design Flow” that is commonly used to create custom silicon/FPGA designs in an industry setting.
This project required me to implement several basic Unix utilities using the C programming language. Implemented utilities include: cat, grep, zip, and unzip. Zip will be altered in a subsequent project to implement multithreading in order to improve efficiency.
In this laboratory, I utilized Cadence Virtuoso to implement a layout cellview for a unit inverter. This required determining the correct size of the NMOS and PMOS transistors based on the FreePDK45 design process library, conforming to all design process rules, and then verifying the functionality of the layout by using Calibre Layout vs Schematic (LVS) verification.
For this project, a 2-input NAND gate was designed and implemented in Cadence Virtuoso, and its performance characteristics were examined by utilizing SPICE simulations. The data obtained from the SPICE simulations were then tabulated, and examined to determine the effectiveness of using logical effort to to measure the propagation delay of the gate.
In this project, I utilized Cadence Virtuoso and Formality ESP to design and test a 2-input AND gate. This gate was created using a 2-input NAND gate and an Inverter, both of which were created as independent cells.