CMOS Inverter Layout
ECE 429 - Intro to VLSI Design
In this laboratory, I utilized Cadence Virtuoso to implement a layout cellview for a unit inverter. This required determining the correct size of the NMOS and PMOS transistors based on the FreePDK45 design process library, conforming to all design process rules, and then verifying the functionality of the layout by using Calibre Layout vs Schematic (LVS) verification.
